高薪工作機會

工作內容：電磁干擾設計工程師主要負責射頻與類比電路信號完整性 (RF/Analog signal integrity) 、電磁干擾 (EMI/EMC) 分析與及封裝天線 (Antenna-in-Package) 設計。藉由開發”晶片+封裝+印刷電路板”共設計流程來解決高整合數位/類比電路的干擾問題，以提供客戶高性價比的 RFSOC/RFSIP 無線通訊 (cellular 4G/5G) 及無線連結 (WiFi, BT, GPS, FM radios) 產品。 1. 射頻與類比電路信號完整性分析與設計 2. 射頻系統單晶片 (RFSOC/RFSIP) 電磁干擾分析與設計 3. 封裝天線設計與驗證 4. “電路+封裝+印刷板” 共模擬平台開發與驗證 5. Design Guide 的撰寫與推廣

工作內容：1. 記憶體電路設計與驗證 2. 記憶體編譯器平台開發

工作內容：1) 開發針對本公司晶片設計所使用的EDA工具,工作內容包含:需求分析,演算法設計,資料處裡,與使用者介面設計 2) 推廣與嵌入新的流程到未來開案的晶片,目標是提升晶片開發的效率與品質 3) 透過設計演算法或以AI技術來定義與解決IC設計流程遇到的難題

工作內容：(1) Verification Planning 1.1 DSP platform module and/or system design 1.2 5G/6G modem module and/or system design (2) Testbench Build-Up 1.1 Constrained random verification by SystemVerilog/UVM usage 1.2 Reference modeling 1.3 Assertion check 1.4 Coverage closure (3) Coordination with Algorithm/Digital design/Software teams

工作內容：1. 高速SerDes IP開發 2. 數位電路設計與晶片整合 3. 訊號處理與通訊演算法實現

工作內容：We are heavily recruiting talents and professionals in DV, EDA, and AI/ML fields to join our force to conquer new heights in chip complexity! As one of the world’s top IC design companies, MediaTek is constantly pushing the capabilities of chips to the limits. Our newest SoCs and ASICs are wildly sophisticated, packed with industry-leading technologies built by thousands of chip designers. With great design power comes great verification responsibilities. Our team, as a part of the verification force, has put major efforts into creating innovative and robust strategies to fulfill these responsibilities. To ensure high design quality for first silicon success, we have implemented a complete suite of functional and low-power test plans and benches across all design scopes, from IPs to SoC integrations. Furthermore, we have been collaborating with EDA tool providers and academic institutions on leveraging new verification technologies, including emulation, AI tuning, and formal methods, many of which have improved the traditional workflows by orders of magnitude. We also keep challenging ourselves to develop in-house verification tools and platforms to accelerate test regressions and track verification progress more efficiently. All these efforts ultimately lead to our success in delivering high-quality chips over the years.

工作內容：1. IC封裝/晶圓凸塊技術開發與管理 2. 與封裝廠合作完成規劃之技術開發 3. 先進封裝技術開發,驗證與生產良率管理 4. 定期與不定期執行bumping/fan-out/WLCSP廠品質稽核

工作內容：1. DSP處理器和相對應的周邊IP驗證環境開發 2. 從module, IP 到system的功能驗證及自動化環境 3. 設計測試pattern以對低耗電及效能做分析 4. Post-silicon 除錯 及 耗電/效能correlation

工作內容：Responsible for digital design verification of power management IC 1. Define verification plan 2. Create testbench and verify design functionality 3. Develop verification environment 4. Explore DV methodology

工作內容：由於 先進製程 與 高整合度晶片 需要 較長的研發時間 及 高製造成本, DV (Design Verification) 已成為 聯發科技 晶片開發流程中 不可或缺的一環 . CDG DV部門負責 開發與執行 最高整合度 Smartphone, TV 與 ASIC 驗證工程. * 內容包含: 整合型驗證環境開發, 大數據分析與效能改善, BUS Fabric / EMI (External memory interface ) / Low power functions 驗證規劃及執行. * 工作中需要 設計 及 精進 Verification plan/methodology/bench, 對 SOC 系統會有整體而深入的了解. * 利用 最新 EDA tool and concept 來完成 你的 驗證計畫. **工作地點:新竹、台北皆可